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<h1><img align="center" height="32" width="32" src="../../../icons/shiftreg.gif">
<em>Schieberegister</em></h1>

<p><table>
<tr><td><strong>Bibliothek:</strong></td>
	<td><a href="index.html">Memory</a></td></tr>
<tr><td><strong>Eingeführt:</strong></td>
	<td>2.3.0</td></tr>
<tr><td valign="top"><strong>Aussehen:</strong></td>
	<td valign="top"><img src="../../../img-libs/shiftreg.png"></td></tr>
</table></p>

<h2>Verhalten</h2>

<p>This register consists of several stages, where each clock may lead to
each stage receiving the value in the previous stage, while a new value is
loaded into the first stage. The component optionally also supports parallel
loads and stores to all stages' values.</p>

<p>The <var>clear</var> input resets all stages to 0 (all
zeroes) asynchronously; that is, as long as the <var>clear</var> input
is 1, all values are pinned to 0, regardless of the clock input.</p>

<h2>Pins</h2>

<p>* An asterisk marks pins that exist only when the Parallel Load attribute
is enabled.</p>

<dl>

<dt>West edge, top pin (input, bit width 1)</dt>
<dd>Shift: When 1 or disconnected, all stages advance with the clock trigger;
but if it is 0, no advance takes place. This input is ignored if the Load
input is 1.</dd>

<dt>West edge, middle pin (input, bit width matches Data Bits attribute)</dt>
<dd>Data: When advancing the stages, the value found at this input is loaded
into the first stage.</dd>

<dt>West edge, bottom pin marked with triangle (input, bit width 1)</dt>
<dd>Clock: At the instant that this is triggered as specified by the
Trigger attribute, the component may advance the stages or load new values.</dd>

<dt>*North edge, left pin (input, bit width 1)</dt>
<dd>Load: When this 1, the values found on the other north-edge pins are
loaded into all stages at the next clock trigger. When 0 or disconnected, no
load occurs.</dd>

<dt>*North edge, other pins (input, bit width matches Data Bits attribute)</dt>
<dd>Data: These values are loaded into all stages when the clock is triggered
while the <var>load</var> input is 1. The leftmost input corresponds to the
youngest stage.</dd>

<dt>South edge, left pin (input, bit width 1)</dt>
<dd>Clear: When this is 1, all stages are asynchronously reset to 0, and all
other inputs are ignored.</dd>

<dt>*South edge, other pins (output, bit width matches Data Bits attribute)</dt>
<dd>Output: Emits the value stored in each stage, with the youngest stage
reflected on the leftmost of the pins (next to the <var>clear</var> input).</dd>

<dt>East edge (output, bit width matches Data Bits attribute)</dt>
<dd>Output: Emits the value stored in the final (oldest) stage.</dd>

</dl>

<h2>Attribute</h2>

<p>When the component is selected or being added,
the digits '0' through '9' alter its <q>Number of Stages</q> attribute
and Alt-0 through Alt-9 alter its <q>Data Bits</q> attribute.</p>

<dl>

<dt>Data Bits</dt>
<dd>The bit width of the value stored in each stage.</dd>

<dt>Number of Stages</dt>
<dd>The number of stages included in the component.</dd>

<dt>Parallel Load</dt>
<dd>If <q>yes,</q> then the component includes inputs and outputs facilitating
parallel access to all the stages' values.</dd>

<dt>Trigger</dt>
<dd>Configures how the clock input is interpreted. The value <q>rising edge</q>
indicates that the register should update its value at the instant when the
clock rises from 0 to 1. The <q>falling edge</q> value indicates that it should
update at the instant the clock falls from 1 to 0.</dd>

<dt>Label</dt>
<dd>The text within the label associated with the component.</dd>

<dt>Label Font</dt>
<dd>The font with which to render the label.</dd>

</dl>

<h2>Verhalten des Schaltwerkzeugs</h2>

<p>If the Parallel Load attribute is no, or if the Data Bits attribute is more
than 4, then poking the register has no effect. Otherwise, clicking the
component will bring keyboard focus to the clicked stage
(indicated by a red rectangle), and typing a hexadecimal digit will
change the value stored in that stage.</p>

<h2>Verhalten des Textwerkzeugs</h2>

<p>Allows the label associated with the component to be edited.</p>

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